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<title>VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values </title></head>
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<h1>VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.128.66.0F38.W0 42 /r</p>
<p>VGETEXPPS xmm1 {k1}{z}, xmm2/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Convert the exponent of packed single-precision floating-point values in the source operand to SP FP results representing unbiased integer exponents and stores the results in the destination register.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F38.W0 42 /r</p>
<p>VGETEXPPS ymm1 {k1}{z}, ymm2/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Convert the exponent of packed single-precision floating-point values in the source operand to SP FP results representing unbiased integer exponents and stores the results in the destination register.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F38.W0 42 /r</p>
<p>VGETEXPPS zmm1 {k1}{z}, zmm2/m512/m32bcst{sae}</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Convert the exponent of packed single-precision floating-point values in the source operand to SP FP results representing unbiased integer exponents and stores the results in the destination register.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Extracts the biased exponents from the normalized SP FP representation of each dword element of the source operand (the second operand) as unbiased signed integer value, or convert the denormal representation of input data to unbiased negative integer values. Each integer value of the unbiased exponent is converted to single-preci-sion FP value and written to the corresponding dword elements of the destination operand (the first operand) as SP FP numbers.</p>
<p>The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location.</p>
<p>EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
<p>Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-sentation). Special cases of input values are listed in Table 5-8.</p>
<p>The formula is:</p>
<p>GETEXP(x) = floor(log<sub>2</sub>(|x|))</p>
<p>Notation <strong>floor(x)</strong> stands for maximal integer not exceeding real number x.</p>
<p>Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD FP exceptions.</p>
<h3>Table 5-8. VGETEXPPS/SS Special Cases</h3>
<table>
<tr>
<th>Input Operand</th>
<th>Result</th>
<th>Comments</th></tr>
<tr>
<td>src1 = NaN</td>
<td>QNaN(src1)</td>
<td>No Exceptions</td></tr>
<tr>
<td>0 &lt; |src1| &lt; INF</td>
<td>floor(log<sub>2</sub>(|src1|))</td>
<td></td></tr>
<tr>
<td>| src1| = +INF</td>
<td>+INF</td>
<td></td></tr>
<tr>
<td>| src1| = 0</td>
<td>-INF</td>
<td></td></tr></table>
<p>Figure 5-14 illustrates the VGETEXPPS functionality on input values with normalized representation.</p>
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<h3>Figure 5-14.  VGETEXPPS Functionality On Normal Input values</h3>
<p><strong>Operation</strong></p>
<p>NormalizeExpTinySPFP(SRC[31:0])</p>
<p>{</p>
<p>// Jbit is the hidden integral bit of a FP number. In case of denormal number it has the value of ZERO.</p>
<p>Src.Jbit (cid:197) 0;</p>
<p>Dst.exp (cid:197) 1;</p>
<p>Dst.fraction (cid:197) SRC[22:0];</p>
<p>WHILE(Src.Jbit = 0)</p>
<p>{</p>
<p>Src.Jbit (cid:197) Dst.fraction[22];</p>
<p>// Get the fraction MSB</p>
<p>Dst.fraction (cid:197) Dst.fraction &lt;&lt; 1 ;</p>
<p>// One bit shift left</p>
<p>Dst.exp-- ;</p>
<p>// Decrement the exponent</p>
<p>}</p>
<p>Dst.fraction (cid:197) 0;</p>
<p>// zero out fraction bits</p>
<p>Dst.sign (cid:197) 1;</p>
<p>// Return negative sign</p>
<p>TMP[31:0] (cid:197) MXCSR.DAZ? 0 : (Dst.sign &lt;&lt; 31) OR (Dst.exp &lt;&lt; 23) OR (Dst.fraction) ;</p>
<p>Return (TMP[31:0]);</p>
<p>}</p>
<p>ConvertExpSPFP(SRC[31:0])</p>
<p>{</p>
<p>Src.sign (cid:197) 0;</p>
<p>// Zero out sign bit</p>
<p>Src.exp (cid:197) SRC[30:23];</p>
<p>Src.fraction (cid:197) SRC[22:0];</p>
<p>// Check for NaN</p>
<p>IF (SRC = NaN)</p>
<p>{</p>
<p>IF ( SRC = SNAN ) SET IE;</p>
<p>Return QNAN(SRC);</p>
<p>}</p>
<p>// Check for +INF</p>
<p>IF (SRC = +INF) Return (SRC);</p>
<p>// check if zero operand</p>
<p>IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);</p>
<p>}</p>
<p>ELSE</p>
<p>// check if denormal operand (notice that MXCSR.DAZ = 0)</p>
<p>{</p>
<p>IF ((Src.exp = 0) AND (Src.fraction != 0))</p>
<p>{</p>
<p>TMP[31:0] (cid:197) NormalizeExpTinySPFP(SRC[31:0]) ;</p>
<p>// Get Normalized Exponent</p>
<p>Set #DE</p>
<p>}</p>
<p>ELSE</p>
<p>// exponent value is correct</p>
<p>{</p>
<p>Dst.fraction (cid:197) 0;</p>
<p>// zero out fraction bits</p>
<p>TMP[31:0] (cid:197) (Src.sign &lt;&lt; 31) OR (Src.exp &lt;&lt; 23) OR (Src.fraction) ;</p>
<p>}</p>
<p>TMP (cid:197) SAR(TMP, 23) ;</p>
<p>// Shift Arithmetic Right</p>
<p>TMP (cid:197) TMP – 127;</p>
<p>// Subtract Bias</p>
<p>Return CvtI2D(TMP) ;</p>
<p>// Convert INT to Single-Precision FP number</p>
<p>}</p>
<p>}</p>
<p><strong>VGETEXPPS (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF (EVEX.b = 1) AND (SRC *is memory*)</p>
<p>THEN</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>ConvertExpSPFP(SRC[31:0])</p>
<p>ELSE</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>ConvertExpSPFP(SRC[i+31:i])</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VGETEXPPS __m512 _mm512_getexp_ps( __m512 a);</p>
<p>VGETEXPPS __m512 _mm512_mask_getexp_ps(__m512 s, __mmask16 k, __m512 a);</p>
<p>VGETEXPPS __m512 _mm512_maskz_getexp_ps( __mmask16 k, __m512 a);</p>
<p>VGETEXPPS __m512 _mm512_getexp_round_ps( __m512 a, int sae);</p>
<p>VGETEXPPS __m512 _mm512_mask_getexp_round_ps(__m512 s, __mmask16 k, __m512 a, int sae);</p>
<p>VGETEXPPS __m512 _mm512_maskz_getexp_round_ps( __mmask16 k, __m512 a, int sae);</p>
<p>VGETEXPPS __m256 _mm256_getexp_ps(__m256 a);</p>
<p>VGETEXPPS __m256 _mm256_mask_getexp_ps(__m256 s, __mmask8 k, __m256 a);</p>
<p>VGETEXPPS __m256 _mm256_maskz_getexp_ps( __mmask8 k, __m256 a);</p>
<p>VGETEXPPS __m128 _mm_getexp_ps(__m128 a);</p>
<p>VGETEXPPS __m128 _mm_mask_getexp_ps(__m128 s, __mmask8 k, __m128 a);</p>
<p>VGETEXPPS __m128 _mm_maskz_getexp_ps( __mmask8 k, __m128 a);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Invalid, Denormal</p>
<p><strong>Other Exceptions</strong></p>
<p>See Exceptions Type E2.</p>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>If EVEX.vvvv != 1111B.</td></tr></table></body></html>